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12/28/2012

Fine Frequency Control using the Philsar PS-XX00 Fractional-N Synthesizers



Many techniques from simple to complex, currently exist for synthesizer frequency output control by manipulating the crystal oscillator to maintain a constant output frequency. All of them have associated cost and parts count considerations. This application note describes how to perform fine frequency control using the Philsar PS-XX00 series fractional-N synthesizers and a VCO. This method is a simple and low cost alternative to pulling the crystal reference frequency in order to manipulate the final output frequency.

Applications 
• Radio Calibration
• Automatic Frequency Control
• Reference Crystal Accuracy
• Reference Crystal Temperature Compensation
• Reference Crystal Aging Compensation
• Doppler Correction

Step Size
The Philsar PS-XX00 family of synthesizers (PS-1200, PS-2500 and PS-6500) has 18-bit fractionality on the main synthesizer giving 262,144 steps with respect to the internal reference frequency. The formula is for calculating the step size is:
 
R is an integer value ranging from 1 to 32 used to divide the crystal reference frequency (FXtal) to arrive at the internal reference frequency (Fref).
Example 1. Using a 20 MHz crystal and a reference division of R = 1 yields,
                
This represents the minimum step size achievable with a 20 MHz crystal oscillator and R=1.

Example 2. Using a 20 MHz crystal and a reference division of R = 32 yields,
                      
This represents the minimum step size achievable with a 20 MHz crystal oscillator and an R value of 32.

Frequency Resolution
Fine resolution can be achieved by having a very fine step size of 2 Hz (R=32) to 76 Hz (R=1) as indicated above. This step size is independent of the output frequency and applies to the PS-1200 and PS-2500. The PS-6500 will have a 4 times greater step size on the main synthesizer due to a fixed divide-by-4 to the divider input. Another way to look at the frequency resolution is in parts per million (ppm) relative to the output frequency. The formula for calculating the resolution in ppm is defined as follows:
                           
Example 3. Calculate the correction in ppm of a 1.9 GHz PLL output by using a 20 MHz crystal and R = 1.
                                  

Radio Calibration
The ability to calibrate a radio or a PLL output using a high resolution fractional-N synthesizer is much simpler than using Automatic Frequency Control (AFC) or characterizing crystal oscillators for temperature drift or aging and offers many advantages. During production, radios must be tuned to perform at expected frequencies within a predetermined tolerance.

Tuning radios can be time consuming and expensive. Frequently radios have a tunable component which is adjusted by a technician to calibrate the radio frequency output. A major reason for this requirement is due to the absolute frequency inaccuracy of the crystal. When a 10 MHz crystal oscillator is purchased there is associated with this part a frequency error. For example, a 10 MHz crystal might actually be 10.000005 MHz. If the value of N is 250, this would mean an output frequency of 2.5 GHz, this would translate to a PLL output inaccuracy of 1250 Hz. This error must be corrected prior to shipping the radio product. Further to this, once the product has been shipped the crystal frequency will also change due to temperature drift and aging.

In other words the frequency output value will constantly be changing. The amount will be dependent upon the type of oscillator being used. Temperature drift and aging of the crystal oscillator are relevant in the field, whereas the initial crystal inaccuracy is an issue in manufacturing.

A common method employed for correcting these problems is to use a Voltage Controlled Crystal Oscillator (VCXO). In this method the system determines that the crystal frequency is either high or low and therefore must be adjusted. A correction is introduced to the crystal to return the output frequency back to its original desired value. This method involves hardware components and software algorithms to perform this correction. A different method is proposed in the AFC section of this application note where the output frequency of the VCO is corrected.

A simpler method to correcting either the crystal frequency inaccuracy or the VCO output is to allow the crystal frequency to drift naturally and perform a calibration of the crystal relative to the output. The method is simple in concept. What we need to do to perform this calibration is to measure the output of the VCO and to perform a simple calculation to determine the actual crystal frequency. Correcting the output of a radio requires more calculations as the different IFs which are system dependent must be brought into the overall equation. If we program a fractional-N PLL to output a given frequency of 2.45617 GHz, then the synthesizer will perform a calculation to determine the actual Fractional-N value required to bring the output of the VCO to 2.45617 GHz based on the value of the crystal frequency using the following formula.
                                 
Example 4. Perform a calibration on a PLL operating at 2.45617 GHz using a 20 MHz crystal and a reference division of R = 2.
Therefore using formula [4]:
                                             
Therefore the required N value for the PLL to produce the desired frequency output is 245.617.

If we then ask the synthesizer to output the desired frequency, the output will be N x internal reference frequency FRef (which is the crystal frequency FXtal divided by the reference divider R) or
approximately 2.45617 GHz. At this point we need to take a measurement of the actual output frequency of the PLL. If the output is determined to be 2.45637 GHz, this tells us that the error in the output is 200 kHz. This also tells us that the crystal value that we have been using is in error. Substituting the measured output for the desired output we are able to calculate the actual crystal oscillator frequency.

                                         
Therefore the actual crystal frequency in the system is 20.001628 MHz, 1628 Hz higher than we expected. The new crystal frequency value would now be placed in non-volatile memory inside the radio to be used for future calculations.

The crystal frequency error can also be expressed in 81.4 ppm as in the following example:                                                                 
If we now use this new crystal frequency of 20.001628 MHz in the calculations using formula [4] we now determine that the new required N value.                                              
                           
Recapping, the actual crystal frequency was determined to be 20.001628 MHz which is a correction of 81.4 ppm. The new N value required in order to achieve the originally desired 2.45617 GHz output is now 245.596. Now that we know that the crystal frequency is actually 20.001628 MHz, we can use this number in all of the frequency calculations until we determine that we need to perform the calibration again. In production, this would mean automating the procedure without the need for tuning elements as all corrections are performed in software.

A key benefit is that radio manufacturers are no longer dependent upon the crystal vendors to manufacture crystals to very tight frequency tolerances as they can simply correct for these by using
a high resolution synthesizer. In fact, similar frequencies can easily be substituted with only small changes in performance due to higher N values. Using this method a 19 or 21 MHz crystal could easily be used. This type of calibration is not limited to final production test. If the radio system that is deployed in the field has a means of determining what the frequency output is, then we could periodically use this method in the radio to self calibration in the field and update the crystal frequency value in the non-volatile memory.

As was stated earlier, since the crystal frequency can be allowed to drift, all that we need to know is what the actual crystal frequency is at any given moment. The factory calibration would have previously corrected for the initial inaccuracy of the crystal oscillator therefore this is the starting point for any future drifting of the crystal frequency. Continuing to perform this calibration method in the field, the effects of aging and temperature drift can be easily corrected for in a TCXO. If the calibration is performed often enough and depending on the system requirements, then perhaps even a free running crystal could be utilized.

With this system calibration method being performed in the field, the system would be able to compensate for any temperature drift without requiring any knowledge of the system temperature.
There are several advantages offered by this method:
• Any similar crystal frequency could be substituted i.e. 24.1 or 23.9 MHz
• The absolute accuracy of the crystal frequency is no longer important as this can be corrected in
  production test
• Crystal aging now can be field corrected
• Temperature correction of the crystal can be performed real time without requiring prior knowledge
  of the temperature characteristics of the crystal or the actual operating temperature of the radio

Automatic Frequency Control
Automatic frequency control is a method of adjusting the output frequency of a PLL up or down, based on the system’s ability to measure the actual operating frequency or the ability to track a
drifting carrier frequency in a remote transmitter. In either case the correction can be performed directly by the synthesizer. If automatic frequency control is being employed, this can alleviate the need to perform any correction because of crystal inaccuracy, temperature drift or aging of either a local receiver or a remote transmitter. Typically, automatic frequency control is achieved by the use of a Voltage Controlled Crystal Oscillator (VCXO). A VCXO is a Crystal Oscillator (XO), a Temperature Compensated Crystal Oscillator (TCXO) or an Oven Controlled Crystal Oscillator (OCXO) with a varactor diode that is controlled by an external voltage. The varactor diode responds to a voltage which corrects the crystal oscillator frequency for crystal accuracy offset, temperature drift or aging effects. VCXOs are typically used in systems with 200 kHz channel spacing or less.

A VCXO has a frequency versus tuning voltage slope and also a linearity associated with this slope. The linearity is specified as the minimum and maximum slopes of the frequency vs. voltage. If a VCXO is operated with large frequency variations, this can cause a stressing which will result in degraded phase noise, aging and temperature stability, thus partially negating the very reasons for having selected a VCXO in the first place. If a system has the capability for correcting the crystal, then it is reasonable to assume that this correction could also be applied to the synthesizer output as well. This has many advantages: First, there is a cost savings as the expensive VCXO can be replaced by a less expensive crystal oscillator. Second, power can be reduced if the PS-XX00 series on-chip
crystal oscillator is used as it consumes much less power than external oscillators. Third, close in phase noise is improved as the phase noise of a crystal oscillator is lower than a typical VCXO. The actual corrections would also be smaller because the crystal is not constantly being corrected (stressed) which can cause further variations in aging, temperature sensitivity and phase noise. Fourth, there is no additional frequency versus tuning voltage slope or the associated linearity to contend with. Large variations relative to a VCXO are well within the normal operation of the PS XX00 series fractional-N synthesizer.

Crystal Characteristics
Crystals made from quartz are available in frequencies typically ranging from 10 to 150 MHz. There are various ways to cut quartz crystals which affect the performance. The “AT” cut has become
the most popular because it can operate at relatively high frequencies and gives excellent frequency versus temperature stability. The typical frequency range of a crystal based on a fundamental is about 30 MHz. Above 30 MHz the cut of the material becomes too thin for practical production. For frequencies above this point, odd integer multiples such as the 3rd, 5th, 7th or 9th overtone ofthe fundamental frequency are used.

Reference Crystal Accuracy
Crystal oscillators vary in accuracy as well. Expensive accurate crystals use a deposition technique to grow the material until crystals reach the desired frequency. These expensive crystals have the same phase noise and temperature characteristics as the inexpensive crystals but have a lower initial frequency offset error. This offset error is usually expressed in tolerance in ppm at room temperature. The actual output frequency can be anywhere within the specified range.
Example 5. Tolerance = +/- 10 ppm @ 25oC

If a low cost crystal with a possible large frequency offset is chosen in the system, then it is possible to correct for this inaccuracy in final test. By performing a measurement of the frequency output of the PLL synthesizer and comparing this with the desired output, then the error can be calibrated out of the system by storing a correction factor in non-volatile memory. The amount of frequency offset seen in a typical system does not exceed the synthesizers ability to perform the correction. The correction factor itself can be placed in a non-volatile memory in the system. This method allows a cost sensitive product such as a multi-mode handset to have an inexpensive crystal.

Reference Crystal Temperature Compensation
The output frequency of a crystal oscillator drifts with the external temperature. This drift is expressed in stability in ppm at room temperature. The frequency versus temperature curve can be seen in Figure 1 on page 4. Typical temperature drift of a crystal can be up to +/- 30 ppm over the operating temperature range.
Example 6. Stability = +/- 30 ppm (-10oC to +60oC)

Temperature compensated crystal oscillators (TCXO’s) have an added thermistor/resistor circuit that drives a varactor diode which is in series with the crystal. This circuit is designed to cancel the crystal temperature characteristics. The circuit will improve the temperature stability of the crystal, however it will never eliminate the temperature drift entirely.

Typical temperature drift of a TCXO can be 2 ppm over the operating temperature range. The Philsar PS-XX00 series of fractional-N synthesizers has an internal crystal oscillator. If a TCXO can be replaced by the internal oscillator and a basic crystal, then a cost and power savings compared with the TCXO can be achieved. Replacing the TCXO means that the crystal temperature characteristics will have to be corrected.
                                                             
 
                                     
Many radio systems now have the system temperature available in software. If we know the temperature, then all that remains is to develop the curve representative of the temperature characteristics of the crystal. The typical curves for the crystal can sometimes be obtained from the manufacturer. With this knowledge the synthesizer frequency output can be adjusted at the VCO via software in the microprocessor or DSP controlling the synthesizer.

If the radio system does not have the ability to measure temperature, then a simple circuit involving a thermistor and a low cost A/D can be utilized. The added cost of this would reduce the cost saving to be had by the elimination of a TCXO, however the designer now has the system temperature in software that can be utilized in other parts of the system. It can be pointed out that crystals do not all have the same temperature characteristics from unit to unit. This is a function more of the tolerances of the oscillator circuitry and the compensation network than of the crystal characteristics. TCXO
manufacturers will typically mark the package with an “offset” frequency either in Hz or ppm. Having the crystal oscillator circuitry in a very repeatable BiCMOS process may minimize the effect.

In any case, just as the TCXO manufacturer can tweak the offset manually, this can be performed as part of the automated test set up, where the actual output at room temperature can be measured and an offset in Hz can be fed into the system memory. Another benefit of performing crystal compensation in software is the fact that the designer is not required to state the operating temperature range when specifying the oscillator, as would be the case with a TCXO. This is because the temperature compensation circuit in a TCXO can not completely compensate for the individual characteristics of the crystal. The manufacturer will only match the thermistor/resistor network to the crystal curve
over the specified temperature range. As seen in Example 3, a 1.9 GHz system using a 20 MHz crystal
can be corrected by 0.04 ppm or by 76 Hz. This can eliminate the requirement for an expensive TCXO reducing the system cost.

Crystal Aging Compensation
Crystal output frequencies drift with time. Aging is caused by thermal effects such as temperature cycling, high ambient temperature or even high drive levels to name a few. The average drift of a crystal can be 2 to 3 ppm per year. This means that after a number of years the crystal may drift so that the VCO output frequency is not in the center of the channel. This can render the PLL and the radio inoperative. The amount of drift that can be tolerated is system dependent. The frequency error per year attributed to aging can be calculated by:
                          
Where DF is the change in the crystal frequency over the period of 1 year.

Example 7. Calculate the total frequency error after 3 years of a 1.9 GHz GSM radio using a 200 MHz high side LO and a crystal that ages 3 ppm per year. Using a 200 MHz high side LO means that the output frequency of  the PLL synthesizer would be 2.1 GHz. Therefore,
                           
Therefore, after 3 years the total drift would be 18.9 kHz. In a GSM system the channel spacing is 200 kHz. This means that after only 3 years, the actual frequency would be approximately 20% away from the center of the channel due to aging alone!

If the GSM handset in Example 7 is part of a multi-mode, multi-band handset that alternately uses (fall-back mode) the AMPS mode, then the errors in AMPS mode could also be calculated.
Example 8. Calculate the total frequency error after 3 years of a 894 MHz AMPS radio using a 45 MHz high side LO and a crystal that ages 3 ppm per year. Using a 45 MHz high side LO means that the output frequency of the PLL synthesizer would be 939 MHz. Therefore,
 
Therefore, after 3 years the total drift would be 8.4 kHz. In an AMPS system the channel spacing is only 30 kHz. Even though the total drift over 3 years is less than what it would be as in the GSM system, relative to the channel spacing, a frequency drift of over 50% has occurred in the AMPS example.

The average drift of a crystal can either be attained by the manufacturer or can be measured. Sample units can be measured over a period of time and statistical results maintained. The longer the period of time over which the tests are performed, the better the crystals can be characterized. This data can be fed into non-volatile memory aboard the system and any corrections can be performed at specific time intervals. Any corrections are performed directly at the VCO.

Doppler Correction
Many of the radio systems employed today, such as cellular phones, pagers and satellite handsets have one or both terminals mobile. This movement causes a change in frequency up or down according to the following formula:
 
Example 9. Calculate the doppler shift of a cellular phone operating at 1.9 GHz and in a vehicle travelling at a rate of 100 km/h.
The 176 Hz shift can be corrected to a resolution of 76 Hz or 2.4 Hz increments as seen in Examples 1 and 2.

In the case of a satellite handset communicating with a Low Earth Orbit (LEO) satellite the doppler shifts can be 25 kHz. Therefore, there is a significant requirement for correcting satellite handsets.
In the case of the cellular example, when the automobile is travelling away from the base station, the doppler shift is subtracted. When the automobile is travelling toward the base station it is added.
One problem associated with doppler correction is that the figure is not a constant. The automobile will often not be traveling directly towards or away from the base station but rather will be at varying angles or at rest. This means that the doppler shift can be anywhere from zero to the maximum value, as calculated above. The amount of inaccuracy that can be tolerated is dependent upon the system requirements. However, the shift in ppm can be calculated by:
 
Example 10. Calculate the doppler shift in ppm with an operating frequency of 1.9 GHz and doppler shift of 176 Hz.
 
We can look at the non-correlated effects of Doppler Shift, Temperature Drift, Crystal Accuracy and Aging. This can be calculated by:

 Example 11.  Calculate the total non-correlated  frequency error by  using the  individual error values from Examples 10, 6, 5 and 7.
                                 The resultant is a non correlated total frequency error of 32 ppm.

Crystal Temperature Characterization
A TCXO can be realized in software by characterizing crystals according to temperature. These crystals can be temperature-characterized by placing them in an oven and measuring the frequency output versus temperature curve over the desired temperature range. The number of temperature points would depend on what the final system accuracy requirement is. Typically a calibration point every one to ten degrees could be utilized. These values can then be used for correcting the output
frequency of the PLL. As seen in Figure 1, the crystal frequency versus temperature curve typically crosses the zero axis at about 25oC. Variations in the load capacitors of the crystal oscillator circuit and the manufacturing tolerances affecting the thickness of the crystal can introduce an initial frequency offset in the frequency versus temperature curve.

In order to reduce the effect of these variations, in final test performed at 25oC, an output frequency can be generated by the PLL synthesizer. The frequency can be measured and compared to the desired frequency. This error would be translated into an offset for the PLL. This value would be placed in non-volatile memory and used to permanently offset the synthesizer output. Alternatively, the correction could be performed as in the Radio Calibration section above, where the error is used to recalculate the crystal reference frequency.












































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12/21/2012

How To Design RF Circuits - Synthesisers



Introduction
Frequency synthesisers form the basis of most radio system designs and their performance is often key to the overall operation. This paper will present an introductory overview of the basic parameters governing the design of a phase locked loop frequency synthesiser and their effects, with the sources of phase noise within a design also being considered. Finally a list of common problems, along with some possible solutions, is giv en in order to assist in the debugging of a non-functional design once assembled.

What is a Synthesiser?
A synthesiser is a device which takes an input, or source, frequency and from it produces an output frequency which is either directly or indirectly related to it. Possible schemes for direct and indirect synthesisers are shown in figure 1.

                       Figure 1 : Direct and indirect synthesisers.

The direct synthesiser, figure 1a), produces an output which is directly proportional to the input, i.e. for an input frequency fIN and a multiplication factor of N, then the output frequency fOUT is given as
                                                   fout = N *f in                                          Equ. 1

where N can be a fractional value (e.g. ¼) as well as an integer value. Combinations of fractional and integer multipliers between the synthesiser frequency source and the output can produce output frequencies with strange multiples such as 10¾. It should be noted that the “multiplier” can be formed of one or more elements. Figure 2 shows how a “x3” multiplication may be done.

                             Figure 2 : “x3” multiplier.

In both the direct and indirect synthesisers shown, it may be necessary to have some form of output filtering. This would ensure that harmonics and other related spurious frequencies, which may cause spurious responses in a receiver or compression in a transmitter power amplifier, are kept to a sufficiently low level.

Indirect synthesisers, shown in figure 1b) and c), operate by “locking” the output of a frequency source, usually a VCO, to that of another, “cleaner” source, know as the reference frequency. The reference frequency usually has better phase noise, particularly at low frequency offsets, and is more stable in terms of drift with temperature, vibration, etc. The additional mixing stages allow for the generation of frequencies which are higher, but require a fine step tuning range. The benefits of this will be addressed later.

Figure 3 shows the basic block diagram of a phase locked loop. The VCO is “locked” to the reference frequency, fref, by dividing the reference, fref, by some integer R, the VCO output, fout, by some integer N, and then comparing the phase of the two signals, generating an error signal. This error signal is then amplified and filtered to remove phase comparison frequency components and modify the phase response of the loop to provide closed loop stability. It is almost always the case that the reference is a higher quality frequency source than the VCO. The output frequency is then given by

.                                                                       f out =  N/R * fref                                    Equ. 2

 
          Figure 3 : Basic diagram of a phase locked loop

The shaded area of figure 3 is usually integrated into a synthesiser IC, although in special cases some or all of these components can be designed as application specific elements, e.g. the N and/or R divider created from ECL logic Dtypes.

Phase Detector Types
The phase detector in a PLL can take many forms, such as an XOR gate (Type 1), a mixer (Type 1) and Dual D-Types (Type 2) amongst many, although the latter is probably the most common. The type is usually predetermined if a single chip synthesiser is used, however for some applications they can be designed using suitably fast logic, such as that used for a divider, although the operational speed requirement is not as severe. For the purposes of this paper, as it deals mainly with integrated synthesisers, references to the phase detector will be assumed to also refer to the action of the charge-pump output used to tune the VCO via the loop filter. However, it should be noted that not all phase detectors have a current output; some have voltage outputs which will change the procedure for the design of some of the loop components, such as the passive loop filter.

Division In The Loop
Fixed division dividers In a loop where the frequency input exceeds either the maximum RF or reference input frequency of a synthesiser it may be necessary to use a fixed divide by M prior to the ÷N or ÷R functions. M has been used to highlight the difference between M and N. N will be referred to as the division performed by the synthesiser IC used to form the basis of the PLL. The value of M will however limit the step size the synthesiser may perform as the output frequency will now be, assuming the M division is prior to the ÷N, of the form

.                                                             fout =M.N / R * fref                            Equ. 3

This results in a minimum step size of M*fcomp. For a fixed division of M=8 and an N range of 3 to 65535, only division ratios of 24, 32, 40,…,524280 can be achieved. If this formed part of synthesiser trying to step in 8kHz, then the phase detector comparison frequency would have to be ≤1kHz.

Dual modulus prescalers
Dual modulus prescalers are a simple way of implementing a high frequency ÷N within a PLL. The division ratios commonly available are 8/9, 16/17, 32/33, 64/65, although using sufficiently fast logic, such as ECL, it is possible to build prescalers of other ratios. Figure 4 shows a general implementation of a dual modulus prescaler.

        Figure 4 : Application of a dual modulus prescaler

The use of a dual modulus prescaler presents a particular limit on the division possible within a loop. For a prescaler with division ratios of A and A+1 the minimum division ratio above which all N values can be accommodated is (A*(A- 1)), i.e. for an 32/33 prescaler the minimum division from which continuous division is available is (32*(32-1)) = 992. Some divisions below 992 are possible, but need to be confirmed. This is an important point, as many synthesiser Ics now incorporate a dual modulus prescaler (e.g. LMX233x series from National Semiconductor and the ADF41/42xx series from Analog Devices).

 Mixers in the division feedback loop
Mixers can be used to aid the division in the feedback loop as shown in figure 1c). The mixer essentially provides a down-conversion in the loop which lessens the amount of actual division required to synthesise the required output. For a reference frequency fref, the division ratios of N and R, and the frequency fmix, applied to the mixer to down-convert the signal; the resulting output frequency, f out, will be

.                                               f out = ( N / R * f ref ) + f mix                       Equ. 4

The main benefit of this method is the improved noise performance due to the reduced division in the loop.

Loop Filter Design
3rd Order Passive Loop Filter
                       Figure 5 : A third order loop filter.

Figure 5 shows the standard third order loop filter used in most synthesisers. This comprises a second order filter section and an RC section providing an extra pole to assist the attenuation of the sidebands at multiples of the comparison frequency that may appear. The values for these components are easily calculated using the following equations [1]


Other sources of equations for designing loop filters are also available such as [2], with comprehensive derivations of many other forms of loop filter given in [3].

Active Filters
If the tuning voltage required for the VCO is higher than the output range of the synthesiser charge-pump, another option is to use an active filter which runs off a higher power supply voltage. An active, third order loop filter is shown in figure 6.

The transfer function of the filter in figure 6 is given by equation 10 [3]. It is also possible to use an op-amp purely as a voltage amplifier following a loop filter of the type shown in figure 5. Great care should be taken when using opamps as loop filters or amplifiers, as they can add significant noise to the synthesiser.

Design Example

Specification                              Requirement

Frequency tuning range           2.33GHz ± 50MHz
Step size                                  500kHz
Phase error contribution         ≤ 3° rms
Lock time                                ≤ 400μs for a ±20MHz step to
                                                ≤ ± 200Hz of final frequency.

From these few parameters, we first need to estimate the loop bandwidth of the synthesiser. Two “rules of thumb” [4], which may help to approximate the frequency of the loop bandwidth, are


From equation 11, the estimated comparison frequency is ≥125kHz. As this is below the synthesiser step size, the comparison frequency will be set to 500kHz which easily meets the requirements of equation 11. With the required switching speed being <400μs, equation 12 predicts an estimated loop bandwidth of ≥6.25kHz in order to achieve lock in time. To ensure the requirement of equation 12 is met with margin, the loop bandwidth will be set to 10kHz.
Where switching time is unimportant, choice of loop parameters will be governed by phase noise and spurious requirements alone.

The follow sections will deal with each of the topics using this specification for all modelling and designs. Using equations 5 to 9, with some of the following details of the synthesiser, VCO and loop parameters

Synthesiser                                                             Analog Devices ADF4212 [5]
Charge pump current (Icp)                                     5mA
Kvco                                                                      45MHz/V
Division range (N)                                                 4560 to 4760
Reference frequency (fref)                                    10MHz
Phase margin                                                         45° (∴ ρ = √2)

the component values for the complete loop filter shown in figure 5 are calculated to be:
C1 = 1nF C2 = 12nF C3 = 180pF   R1 = 1.8kohm  R2 = 5.6k ohm

Open Loop Analysis
In order to have confidence in the stability of the synthesiser, an open loop analysis is performed to estimate the gain and phase margins. The analysis of theses parameters was performed using the ICAP/4 Windows spice simulator by Intusoft. Similar simulations have been carried out, with the same degree of success using Mathcad, Matlab and MS Excel.

                  Figure 7 : Bode plots showing open loop gain and phase.

The gain margin is defined as the magnitude of the reciprocal of the open-loop transfer function at the frequency where the phase angle is -180°, and is a relative measure of stability. From the phase plot in figure 7 we see there is 180° phase shift at ≈100kHz. The gain margin is the value at this offset on the gain plot of figure 7. In general it is desirable for this value to be greater than 15dB, the reading in this case being ≈25dB.

The phase margin is defined as 180° plus the phase angle of the open loop transfer function at 0dB, or unity, gain. This is also a measure of relative stability. From the gain plot in figure 7, we can see that 0dB gain occurs at ≈13kHz, which corresponds to a phase margin of ≈48°. Phase margin values of ≥30° are usually sufficient.

Closed Loop Analysis

Frequency Response
To check that the closed loop performance is approximately that required we can analyse the frequency response of the loop. This was also performed using spice, the circuit diagram of which is shown in figure 8. This is a very simple model of a PLL, in fact the open loop analysis was done with the same circuit, with the link back to the phase detector model broken in order to “open” the loop. However, this linear approximation provides an adequate model of a PLL in order to have confidence that the design is close to that required. As with the open loop response, the simulation of the closed loop can be done using Mathcad, Matlab or MS Excel.

             Figure 8 : Closed loop spice simulation of PLL synthesiser.

Figure 9 shows the closed loop frequency response of the synthesiser. This shows the gain response peaking, at about 3.3dB, at the loop bandwidth of 10kHz. If the peak is at 3dB, then this is an indication that the phase margin is 45°. Much greater peaking can be an indication of too little phase margin.

                Figure 9 : Closed loop frequency response of figure 8.

Transient Response
Figure 10 shows the transient response of the synthesiser to a step change in frequency of 20MHz. The y-axis is scaled in 1kHz/division, centred on 20MHz. The y-axis of the plot has been normalised to the final frequency of the VCO after the step response has been applied. The step response is applied at t=100μs. From this it is apparent that the loop has settled to the requirement of ≤200Hz of final frequency at ≈320μs.

 
                        Figure 10 : Synthesiser transient response.

Measurements of the actual synthesiser indicate that, for a frequency excursion of ±20MHz, the lock time is ≈150μs,  which is  well  below  both the simulated  value  and the  requirement.  A plot of the synthesiser  output at  2.33GHz is  shown in  figure 11.  The  effect  of the  PLL  is  clearly visible as “shoulders” starting at the loop bandwidth, 10kHz.

 
                    Figure 11 : Synthesised 2.33GHz spectrum.

Phase Noise

What is phase noise?
Although a full treatment is beyond the scope of this paper, the simple definition of phase noise used in this paper is that it is the energy introduced to the spectrum of an oscillator at frequency offsets either side of a carrier frequency, fc, due to the effects of random phase and frequency modulation. Thinking of a perfect sine wave, imagine that the zero crossing points are not consistent and instead have a random element to their position. This randomness will spread the spectrum of the sine wave, such that the spectrum no longer looks like a single line, see figure 12. The four major causes [3] of phase noise in oscillators are f-1 noise or flicker noise, thermal FM noise, flicker phase noise and the
thermal noise floor, although there are other contributions.

Referring to figure 12, we can see the “perfect” frequency source fc (i.e. a single line), the typical phase noise profile of an oscillator and the single sideband noise power in a 1Hz bandwidth.

                      Figure 12 : Graphical description of phase noise.

The measure of phase noise is the difference between the absolute power level, Pfc, of the VCO at frequency fc and the single sideband noise power, Poffset, at an offset frequency, foffset, in a specified bandwidth (usually 1Hz). This gives the equation for phase noise at any given offset as

with the units of the phase noise in dBc/1Hz (usually written as dBc/Hz) and P(fc)  and P(foffset) in dBm and dBm/Hz respectively. A comprehensive treatment of this extensive topic is given in [7].

Sources Of Noise From Within The Loop
Figure 13a) shows a simplified profile of the phase noise at the output of a PLL synthesiser.

 
                      Figure 13 : Phase noise contributions in a PLL.

The action of the phase locked loop on phase noise is that of a low pass or high pass filter, see figure 13b), depending on whether the noise contributions are below or above the loop bandwidth respectively. At offset frequencies »f BW it is usual for the dominant noise contribution to be the VCO phase noise. At offsets «fBW the main noise contribution comes from the reference frequency source, although this is limited by the noise floor of the dividers in the loop. In the region where the offset frequency is close to the loop bandwidth the noise levels are a combined contribution of both of these noise sources.

For synthesiser ICs with integrated dividers, the noise level can be normalised to an N value of 1 and a comparison frequency of 1Hz, called the phase noise index [8]. This index varies with each manufacturer and synthesiser. Some typical values of this index are given in table 1.

 
         Table 1 : Typical phase noise index values for some synthesisers.

The synthesiser noise level within the loop bandwidth can be approximated by

where the phase noise is in dBc/Hz. Using equation 14 with N=(2.33GHz/500kHz)=4660 and f comp=500kHz, the phase noise at 5kHz offset is predicted to be –86.6dBc/Hz The measured result is shown in figure 14 as –84.8dBc/Hz.

 
                    Figure 14 : Design example phase noise at 5kHz.

Other Noise Sources
There are other sources of phase noise that need to be considered when designing a PLL. One of the most common sources of noise is the power supply to the synthesiser. This can be caused in many ways, but most commonly are due to supply ripple and electric or magnetic coupling. Also, if there are any wire-wound components such as inductors or transformers in the design, these can act as mini antennas. Correct PCB Layout of the PLL components relative to each other, and to other circuit areas, is critical to ensure good noise performance. For example putting a high performance synthesiser next to a switch mode power supply may prove disastrous.

Design Example Phase Noise Analysis
The measured phase noise of the example is given in table 2.

                    Table 2 : Synthesiser phase noise measurements.

The rms phase error contribution of the synthesiser over a specified bandwidth may be calculated using equation 15.

where
ϕ                    : RMS phase error (in rad. rms.)
fstart, fstop    : Offset frequency limits
Y(f)               : Single sideband phase noise profile in dBc/Hz

Using equation 12, we find that the rms phase error for the synthesiser is approximately 0.91°. This is well inside the specification of ≤3°.

In summary this means that for an optimum overall phase noise profile the following design aims should be considered

- Use a good quality reference source.
- Try to set the loop bandwidth such that the level of the plateau in the noise profile meets the VCO   phase noise at the same point.
- Use a low noise VCO.
- Try to reduce the overall division in the loop. As the noise within the loop goes up by 20*Log10(N), keeping N low is important. For high frequency synthesisers requiring fine stepping consider architectures such as that in figure 1b) and c).
- Know your system’s tolerance to phase noise and design only to meet this requirement. Trying to achieve excellent noise performance at all offsets will affect design time, and increase cost and complexity.
- Most importantly, look at the synthesised output on a spectrum analyser. The only real way to know  what you’vegot is if you look at it !!

My Synthesiser Doesn't Work As Expected, Why?
After the synthesiser has been designed and built, there may be a few areas of the design which are not performing as required. Some of the more common problems are addressed below, with some of their possible causes, although it is always wise to check that the DC conditions are correct first, i.e.

- Are the power supplies correct and are they present on the synthesiser?
- Is the power supply current limiting or oscillating?

The synthesiser does not lock.
- Check that the VCO output is connected to the synthesiser RF input, and that the level is adequate.
- Check that the VCO is oscillating
- Check that the synthesiser is being programmed correctly.

The synthesiser does not lock in time.
• Is the bandwidth of the loop filter correct?
• Is the charge pump current set correctly?
• Do the capacitors in the loop filter have an excessive leakage current?
• As with the previous point, any residual flux left during soldering around the loop filter can also
provide a leakage path for the current output of the charge pump.

The spectrum contains many spurious frequencies
• Are any inductors in the loop filter, VCO, etc. acting as antennas or "pick-ups" for high level RF
signals in close proximity.
• Is the power supply to all the elements of the PLL well filtered and decoupled. Bench power supplies are notorious sources of noise. If possible, run the circuit from a battery supply.
• Is the synthesiser reference "clean"? Any spurious signals at the reference input will be subjecte d to a gain of 20*Log(N/R), modified by the loop filter shape.

The loop bandwidth is not as expected
• Have the loop components been calculated correctly? It is a common mistake to miss out factors of 2π (or add too many!!)
• If an active loop filter has been used, check that the op-amp does not introduce any poles which may
alter the filter characteristic.
• Is the charge pump current set correctly?

The phase noise is higher than expected
• Is the phase noise of the synthesiser reference oscillator “clean”?
• Has the expected noise floor within the loop bandwidth been calculated correctly, i.e. using
20*Log(N)?
• Is the VCO oscillating correctly and not "multi-moding" (i.e. oscillating at more than one frequency at the same time)?
• If an active filter has been used, is it adding more noise than expected?
• The thermal noise contributions of large value resistors, used in the loop filter, can add to the overall
noise of the synthesiser. Keep them as small as possible.

Summary
This paper has presented a simple overview of the basics of PLL synthesiser design, with particular reference to the use of integrated synthesiser ICs. Approximations of the frequency and transient responses and phase noise profiles have been shown and then applied to a design to show that they can produce a “real world” design. However, it should be noted that the topic of synthesisers is a vast one and it is far beyond the scope of this paper to cover all the design aspects. Every synthesiser design should be carefully assessed in its own right and careful calculations carried out to model any system critical areas on which the synthesiser characteristics may have an impact.

References
[1] Hughes, P. “Low power single/dual frequency synthesisers”, Philips Semiconductors Application Note AN95102, 1995.
[2] Keese, W.O. “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops”, National Semiconductor Application Note AN1001, 1996.
[3] Rohde, U.L. “Microwave and Wireless Synthesisers – Theory and Design”, 1997, ISBN 0-471-52019-5.
[4] Smithson, G. “Synthesised Frequency Sources in Digital Cellular Handsets”, Microwaves and RF 1997 Conference Proceedings, pp 124 – 130.
[5] ADF421x Dual Frequency Synthesiser Preliminary Technical Datasheet. Analog Devices.
[6] DiStefano, J. et. al. “Theory and Problems of Feedback and Control Systems”, 1990, ISBN 0-07-017047-9.
[7] Robins, W.P. “Phase noise in signal sources”, 1998, ISBN 0-86341-026-X.
[8] Banerjee, D. “Understanding Phase Noise and Lock Time in PLL Designs”, May 1999 Featured Article, www.rfglobalnet.com











































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